1. Field of the Invention
The present invention is directed toward the field of circuits, and more particularly toward active shunt-peaked circuits.
2. Art Background
Data communication systems transport data at a speed defined by a predetermined data rate. The speed of transmitting data in modern broadband communication systems has rapidly increased in recent years. Today, data rates as high as 40 giga bits per second (“Gbps”) are required for the OC-768 optical networking standard.
These data communication systems include basic digital circuits, such as multiplexors, demultiplexors, and constituent logic gates. Thus, to operate at high data rates, the digital circuits must also switch at high speeds (i.e., the digital circuits require a high bandwidth of operation). In addition to operating at high speeds, the digital circuits must be designed to minimize power dissipation. Excessive power dissipation degrades integrated circuit performance by producing excessive heat.
Typically, high-speed logic circuits are designed based on bipolar emitter-coupled logic (“ECL”) or metal oxide semiconductor (“MOS”) current-mode logic (“CML”). These logic families operate using differential inputs, clocks and outputs. FIG. 1 illustrates the conventional implementation of a current mode logic latch.
The digital logic circuits must be able to regenerate signals, so that multiple stages of digital circuits may be cascaded. As shown in FIG. 1, the CML latch circuit includes gain resistors RL1 and RL2. To this end, gain resistors are used on digital logic circuits (e.g., ECL and CML) to maintain a direct current (“DC”) voltage swing on the drain of transistors 103, 104, 105, and 106.
One objective in designing high-speed logic circuits is to reduce the resistive-capacitive (“RC”) time constant at the output of the logic gate. The RC time constant is a product of the resistance, provided by the gain resistors, and the total capacitance at the output of the logic gate. A large RC time constant results in relatively slow rise times of the output signal voltage. In turn, the slow rise time limits the operating speed of the circuit. Thus, the time constant at the output of the logic gate dictates how fast the logic circuit may operate.
One technique for reducing the time constant in the output of the digital circuits is to reduce the gain resistors (e.g., RL1 and RL2 for the latch of FIG. 1). However, if smaller gain resistors are used, the current flowing in the device must be increased in order to maintain the requisite voltage swing at the output of the gate. Thus, in order to attain the necessary increase in current, an increase in the device size is required. These larger device sizes, in turn, increase the load capacitance (input capacitance of a subsequent gate as well as drain capacitance internal to the gate), and therefore there is no enhanced speed performance of the gate.
Accordingly, it is desirable to provide digital logic circuits that maintain adequate output drive while switching at very high data rates. It is also desirable to provide digital logic circuits with increased performance that minimize power dissipation, device size and inter-symbol interference.